1. Field of the Invention
The present invention relates generally to the field of computer systems, and specifically, to a method and apparatus for dynamically changing draining priority of a receive FIFO.
2. Background Information
Generally, first-in/first-out devices ("FIFOs") are used to buffer data that originates from one bus architecture and is targeted to a device in another bus architecture. For example, a computer system may include a processor, memory, and one or more peripheral devices coupled together by a first bus architecture (e.g., a system bus). A second bus architecture may include a serial peripheral bus (e.g., a universal serial bus "USB", a 1394 serial bus, IEEE 1394-1995 High Performance Serial Bus IEEE, 1995, etc.) with one or more peripheral devices coupled thereto. A bus bridge containing FIFOs therein is typically used to bridge and buffer transactions between the first and second bus architectures.
Data that is received in a receive FIFO from a peripheral device on the serial bus must be placed in memory for processing by the processor. If data is not placed in memory fast enough, a data over-run condition may occur (i.e., when data is received by a full FIFO to cause data already contained therein to be overwritten). Typical prior art receive FIFOs generate a request to drain the FIFO into memory when the FIFO becomes almost full (e.g., 90% full) and do not appear to have any programmable features to change this. However, before data can be drained from the FIFO into memory, access to the bus is required. The time that it takes to gain access to the bus (referred to as "bus latency") is non-deterministic and depends on several factors including the bus speed, the number of devices requesting access to the bus, and the like. Thus, since the bus architecture is susceptible to bus latencies and the serial peripheral device that is originating the data cannot be throttled, an over-run condition may occur, thereby resulting in a loss of data.
The depth of the receive FIFO is one factor in determining the bus latency that the FIFO can handle without an over-run condition occurring. The issue of bus latency is exacerbated by the fact that prior to writing data from the receive FIFO into memory, one or more commands may need to be fetched from memory. That is, a typical data packet received in a FIFO may require a command fetch, data storage, and status write-back, all to different locations in memory.
One possible solution is to provide first and second FIFOs where when one FIFO becomes full with data, the data is switched to the other FIFO while the first FIFO drains. However, this possible solution requires two buffers which adds complexity to the system and decreases the granularity for draining the FIFOs. Moreover, this solution may still cause an over-run condition when using a high speed serial bus (e.g., a 1394 serial bus).
Accordingly, there is a need for a method and apparatus to dynamically change draining priority of a receive FIFO to prevent data over-run conditions.